Recently, a variety of high-performance electrical equipment, such as computer systems and mobile phones, have been developed rapidly and come to be used widely. Such electrical equipment often employs a power-on reset circuit to set the electrical equipment in an initial state to achieve stable operation when the power is turned on. More specifically, a power-on reset circuit resets internal circuits to an initial state to avoid erroneous operation.
As one example, FIG. 1 is a known power-on reset circuit disclosed in the JP-2003-032088-A.
As shown in FIG. 1, the power-on reset circuit includes an operating voltage setting circuit 11, a charging circuit 12, inverters INV11, INV12, and INV13, and a second capacitor C12. The inverters INV11, INV12, and INV13 are connected in series. The operating voltage setting circuit 11 includes a P-type MOS transistor P11 and a depression-type N-type MOS transistor ND11.
The charging circuit 12 includes a pair of P-type MOS transistors P12 and P13 and a first capacitor C11. One terminal of the first capacitor C11 is connected in series to the pair of P-type MOS transistors P12 and P13.
A gate of the P-type MOS transistor P11 is connected to a gate of the P-type MOS transistor P12. Sources of the P-type MOS transistor P11, P12, and P13 are commonly connected to a power supply (a power supply voltage Vcc). Further, a source of the N-type MOS transistor ND11 and another terminal of the first capacitor C11 are connected to ground.
As for the inverters INV11, INV12, and INV13, an input terminal of the inverter INV11 is connected to a junction node between the first capacitor C11 and drains of the P-type MOS transistors P12 and P13 from which a voltage signal (B1) is output. The output terminal of the inverter INV13 is connected to a gate of the P-type MOS transistor P13. The second capacitor C12 is connected between an input terminal of the inverter INV11 and an input terminal of inverter INV13. The inverter INV13 outputs a power-on reset signal POR.
Referring to changes in voltage shown in FIG. 2, operation of the power-on reset circuit of FIG. 1 will now be described.
FIG. 2 shows graphs representing changes in voltage with time of the power supply voltage Vcc and notable nodes of the power-on reset circuit shown in FIG. 1.
After power is supplied (refer to Vcc voltage in FIG. 2), the power supply voltage Vcc is increased gradually. When a difference voltage between the power supply voltage Vcc and a gate voltage of the P-type MOS transistor P11 exceeds a threshold voltage of the P-type MOS transistor P11, the operating voltage setting circuit 11 outputs a first output voltage at an output terminal of the P-type MOS transistor P11. The first output voltage is a lower voltage than the power supply voltage Vcc by a predetermined voltage. The first output voltage is input to a gate of the P-type MOS transistor P12 (B1 voltage wave in FIG. 2).
The P-type MOS transistor P12 is controlled by the first output voltage from the operating voltage setting circuit 11 to have a constant impedance, and starts to charge the first capacitor C11.
The output voltage (B1) at an output terminal of the charging circuit 12 is increased after some delay from the increase of the power supply voltage Vcc.
Since the output voltage (B1) at an output terminal of the charging circuit 12 is a low level initially, an output voltage (B2) of an output terminal of the inverter INV11 is a high level, an output voltage (B3) of an output terminal of the inverter INV12 is a low level, and an output voltage (POR) of an output terminal of the inverter INV13 is a high level. Accordingly, a power-on reset operation is started (OR voltage wave in FIG. 2).
With the charging of the first capacitor C11 the output voltage (B1) at an output terminal of the charging circuit 12 exceeds a logic threshold voltage of the inverter INV11 and the output voltage (B2) of the inverter INV11 changes from a high level to low level. The logic threshold voltage of the inverter INV11 is approximately half of the power supply voltage Vcc in the example circuit of FIG. 1 (B2 voltage wave in FIG. 2). Then, an output voltage (B3) of the output terminal of the inverter INV2 becomes a high level (B3 voltage wave in FIG. 2). Then, an output voltage (POR) of an output terminal of the inverter INV13 becomes a low level (POR voltage wave in FIG. 2). Accordingly, the power-on reset operation is released.
When an output voltage (POR) from an output terminal of the inverter INV13 becomes a low level, the P-type MOS transistor P13 is switched on. Accordingly, the impedance of the charging circuit 12 becomes low, resulting in a small time constant CR.
As a result, the output voltage (B1) at an output terminal of the charging circuit 12 is increased rapidly to a voltage almost equal to the power supply voltage Vcc. After that, the output voltage (B1) at an output terminal of the charging circuit 12 is kept at a high voltage above the logic threshold voltage of the inverter INV11 without dropping down. Accordingly, it is possible to avoid an erroneous operation.
Using the known power-on reset circuit described above, it may not be possible to obtain a stable operation when a rising speed of power supply voltage is slow. More specifically, when the rising speed of power supply voltage is slow, it is necessary to design the time constant of the charging circuit large so that the rising time of the output voltage (B1) at an output terminal of the charging circuit 12 becomes slow. As a result, it becomes possible to output the power with the reset signal POR reliably. Since the time constant of the charging circuit is determined by the P-type MOS transistor P12 and the capacitance of the capacitor C11, it is necessary to make the capacitor C11 large. Further, the duration of the high level of the power-on reset signal may vary due to irregularities arising during the manufacturing process and may not be enough to perform the power-on reset operation.